TC9802P

Manufacturer	TOSHIBA CORP
Part Package Code	DIP
Package Description	0.300 INCH, PLASTIC, DIP-20
Pin Count	20
Reach Compliance Code	unknown
HTS Code	8542.39.00.01
Additional Feature	8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PLA-TYPE
Clock Frequency-Max	14 MHz
JESD-30 Code	R-PDIP-T20
JESD-609 Code	e0
Length	24.6 mm
Number of Dedicated Inputs	8
Number of I/O Lines	9
Number of Inputs	18
Number of Macro Cells	8
Number of Outputs	9
Number of Terminals	20
Operating Temperature-Max	85 °C
Operating Temperature-Min	-40 °C
Organization	8 DEDICATED INPUTS, 9 I/O
Output Function	MACROCELL
Package Body Material	PLASTIC/EPOXY
Package Code	DIP
Package Shape	RECTANGULAR
Package Style	IN-LINE
Programmable Logic Type	EE PLD
Propagation Delay	40 ns
Qualification Status	Not Qualified
Seated Height-Max	4.45 mm
Supply Voltage-Max	6 V
Supply Voltage-Min	2 V
Supply Voltage-Nom	5 V
Surface Mount	NO
Technology	CMOS
Temperature Grade	INDUSTRIAL
Terminal Finish	TIN LEAD
Terminal Form	THROUGH-HOLE
Terminal Pitch	2.54 mm
Terminal Position	DUAL
Width	7.62 mm

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